ISSN (Online) : 2456 - 0774

Email : ijasret@gmail.com

ISSN (Online) 2456 - 0774

DESIGN OF LOW POWER AND AREA EFFICIENTMULTIPLIERS USING ADVANCED GDI METHOD

Abstract

Abstract: Today, more and more, high speed mobile computational devices and equipments are being introduced in themarket. These computational devices strain and drain the battery very quickly. Researchers are making efforts to find waysand means to conserve the battery power for longer period. The core key components in these computational devices are theMultipliers to support high speed computational intensive applications in real time. Thus it becomes more important toreduce power dissipation and area in these multiplier modules as they affect the performance of the device. Several VLSIdesign techniques have been attempted to optimize the power and area occupied by the multiplier module, but there arevery few design techniques that gives the required extensibility both in terms of power and area. In this paper a high speed,reliable and efficient multiplier VLSI module design is presented using GDI (Gate Diffusion Input) technique, addressingboth power consumption and area complexity. Further, comparative study results of the proposed design over thetraditional CMOS design are also presented. Detailed design steps and comparative study using Tanner simulation tool at25nm CMOS technology is discussed. The simulation results presented show reduction in both power and area of theproposed design compared to state of art approaches.Keywords: GDI, FA, MULT

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