ISSN (Online) : 2456 - 0774

Email : ijasret@gmail.com

ISSN (Online) 2456 - 0774


DESIGN OF NETWORK ON CHIP BASED CDMA ENCODER WITH WB-SB DECODERS

Abstract

On-chip interconnects are the overall performance bottleneck in contemporary system-on-chips. Code-department multiple get admission to (CDMA) has been proposed to enforce on-chip crossbars because of its fixed latency, decreased arbitration overhead, and higher bandwidth. In CDMA, medium sharing is enabled inside the code space by way of assigning a restrained quantity of N-chip length orthogonal spreading codes to the processing factors sharing the interconnect. In this project, we increase overloaded CDMA interconnect (OCI) to decorate the ability of CDMA Network-on-chip (NoC) crossbars by increasing the wide variety of usable spreading codes. Serial and parallel OCI architecture versions are supplied to adhere to one-of-a-kind place, postpone and energy necessities. Compared with the traditional CDMA crossbar, on a Xilinx Artix-7 AC701 FPGA package, the serial OCI crossbar achieves 100% better bandwidth, 31% less aid utilization, and forty five% energy saving, even as the parallel OCI crossbar achieves N times higher bandwidth compared with the serial OCI crossbar on the cost of elevated vicinity and energy intake. A 65-node OCI-based totally big name NoC is implemented, evaluated, and compared with an equivalent area department a couple of get right of entry to totally based on NoC for various artificial site visitors’ styles. The evaluation effects in phrases of the aid usage and throughput spotlight the OCI as a promising era to enforce the bodily layer of NoC routers.
Index Terms:
Code-division multiple access, overloaded CDMA interconnect, Xilinx, Network-On-Chip.

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Paper Submission Open For September 2020
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Last date for paper submission 30 September , 2020
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