ISSN (Online) : 2456 - 0774

Email : ijasret@gmail.com

ISSN (Online) 2456 - 0774


DESIGN OF AREA EFFICIENT AND LOW POWER 4-BIT MULTIPLIER BASED ON TG

Abstract

Abstract:- With the rapid advancement intechnology, a wide range of high speed mobile computational devices andequipment’s are being introduced in the market. These computational devicesstrain and drain the battery very quickly. Researchers are making efforts tofind ways and means to conserve the battery power for longer period. The corekey components in these computational devices are the Adders and Multipliers tosupport high speed computationally intensive applications in real time. Thus,it becomes more important to reduce power dissipation and area in these Addersand multiplier modules as they affect the performance of the device.  This paper presents a design of 4-bitmultiplier using full adder cell based on transmission gate adder technique.The proposed adder design consists of a smaller number of transistors comparedwith full swing gate distribution technique. Therefore, the complete design ofthe complete adder dissipates the reduced power, while improving the area andensuring a complete output voltage. The fully proposed adder used to design theArray, Baron and Baugh Wooley multipliers, the power and transistor number ofthese multipliers has improved compared to the full swing gate diffusiontechnique.

Keywords— FS XOR-XNOR; FS-GDI; Full Adder;Multiplier; MUX; GDI.


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