ISSN (Online) : 2456 - 0774

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ISSN (Online) 2456 - 0774



Abstract:-In Digital Image Processing, Median Filter is used to reduce the noise in animage. The median filter considers each pixel in the image and replaces thenoisy pixel by the median of the neighbourhood pixels. The median value iscalculated by sorting the pixels. Sorting in turn consists of comparator whichincludes adders and multiplier. Multiplication is a fundamental operation inarithmetic computing systems and is used in many DSP applications such as FIRFilters. The adder circuit is used as a main component in the multipliercircuits. The Carry Save Array (CSA) multiplier is designed by using theproposed adder cell based on multiplexing logic. The proposed adder circuit isdesigned by using Shannon theorem. The multiplier circuits are schematised andtheir layouts are generated by using VLSI CAD tools. The proposed adder basedmultiplier circuits are simulated and results are compared with CPL and othercircuit designed using Shannon based adder cell in terms of power and area andthe intermediate state involved in the circuit is eliminated. The proposedadder based multiplier circuits are simulated by using 90nm feature size andwith various supply voltages. The Shannon full adder circuit based multipliercircuits gives better performance than other published results in terms ofpower dissipation and area due to less number of transistors used in Shannonadder circuit.

Keywords:Half adder, Arraymultiplier, Booth’s Multiplier, Vedic Multiplier, Vedic Mathematics.

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