ISSN (Online) : 2456 - 0774

Email : ijasret@gmail.com

ISSN (Online) 2456 - 0774


DESIGN AND COMPARISON OF RADIX-2 FFT WITH DIFFERENT ADDERS AND MULTIPLIER COMBINATIONS

Abstract

Abstract: There are many advancements in the design and implementation of Fast Fourier Transform (FFT) to improve its speed, reduction in area and power dissipation in view of its applications in signal processing, image processing and communication systems. In this paper radix-2 Decimation in-Time (DIT) FFT architecture is implemented. In this work, the processing element is designed with different adders and multipliers to implement four point radix-2 FFT architecture. The proposed architecture is implemented in verilog code and synthesized using Xilinx ISE 14.7.The performance analysis of FFT architecture is evaluated in terms of number of LUT’s, number of flipflops, total number of slices, maximum path delay and dynamic power dissipation. It is evident from the results that the power dissipation is low in the FFT architecture implemented with Vedic Multiplier (VM) and Carry Select Adder (CSLA). Delay and area is reduced if FFT is implemented using booth multiplier (BM) and kogg stone adder (KSA).Keywords--- FFT, Radix-2, DIT, Butterfly, Multiplier, Adder.

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