Abstract

Abstract: This research work proposes the Vedic multiplier architecture with different carry look ahead adders like regularcarry look ahead adder (RCLA), block carry look ahead adder (BCLA), factorized regular carry look ahead adder(FRCLA), factorized block carry look ahead adder (FBCLA). The Vedic multipliers architecture was designed andsynthesized using Xilinx ISE Design suite. Initially the Vedic multiplier was implemented using regular carry look aheadadder and replaced with other adders and the synthesis parameters were compared. After the comparison we have observedthat the FRCLA is the best one in terms of area and BCLA is the best one in terms of delay