Abstract

Abstract: : Redundant Binary Partial Product Generator technique areused to reduce by one row the maximum height of the partial product arraygenerated by a radix16 Modified Booth Encoded multiplier, without any raise in thedelay of the partial product creation Block. In this paper, we describe anoptimization for binary radix-4 modified Booth recoded multipliers to reducethe maximum height of the partial product columns to [n/4] for n = 64-bitunsigned operands. This is in contrast to the conventional maximum height of[(n + 1)/4]. Therefore, a reduction of one unit in the maximum height isachieved. This Arithmetic multipliers increase the performance of ALU andProcessors. We evaluate the proposed approach by comparison with Normal BoothMultiplier. Logic synthesis showed its efficiency in terms of area, delay andpower. Simulation results show that the proposed Multiplier based designssignificantly improve the area, delay and power consumption when the wordlength of each operand in the multiplier is 64 & n-bits. The proposedarchitecture of this paper analysis the delay and area using Xilinx 14.2.