Abstract:- As technology scales down into the lower nanometer values power, delay, area and frequency becomes important parameters for the analysis and design of any circuits. As technology scales down into the less nanometer values power, delay, area and frequency becomes important parameters for the analysis and design of any circuits. In this paper, an asynchronous parallel self timed adder based on a recursive formulation for performing multi bit binary addition is being implemented. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fanouts. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using industry standard toolkits that verify the practicality and superiority of the proposed approach over existing asynchronous adders.
Keywords: Half adder, Array multiplier, Booth’s Multiplier, Vedic Multiplier, Vedic Mathematics.