ISSN (Online) : 2456 - 0774

Email : ijasret@gmail.com

ISSN (Online) 2456 - 0774

DESIGN OF HYBRID APPROXIMATE ADDERS FOR ENERGY-EFFFICIENT APPLICATION 

Abstract

Abstarct : Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Simple yet Accuracy Reconfigurable adders are discussed and the performance parameters of adders such as area and delay are determined and compared. Various adders are designed using Verilog in Virtex-6 FPGA devices. Then, they are simulated and synthesized using Xilinx ISE 14.2 for Virtex-6 family device with speed grade -2.

Keywords : Ripple Carry Adder; Carry Skip Adder; Carry Increment Adder; Carry Look Ahead Adder; Carry Save Adder; Carry Select Adder; Carry Bypass Adder.

Full Text PDF

IMPORTANT 

Submit paper at ijasret@gmail.com

Paper Submission Open For November 2020
UGC indexed  2017-2019
Last date for paper submission 15 December , 2020
Deadline Submit Paper any time
Publication of Paper Within 01-02 Days after completing all the formalities
Paper Submission Open For online Conference 
Publication Fees(6 Authors) Rs.1000    (Up to 06 Authors)