ISSN (Online) : 2456 - 0774

Email : ijasret@gmail.com

ISSN (Online) 2456 - 0774


AN ENERGY EFFICIENT HIGH SPEED ECRL BASED FULL ADDER DESIGN

Abstract

Abstract:- This project presentsthe high speed and area achieved using the Coordinate Rotation Digital Computer(CORDIC) algorithm for digital signal processing applications. There are manyefficient algorithms for CORDIC, these algorithms there are shifters, adders,and subtractors for sine/cosine wave generation. In this project we proposedmultiplexers based CORDIC algorithm. Multiplexers based Coordinate RotationDigital Computer algorithm used to achieve the fast and efficient hardware onFPGA. A six-stage Coordinate Rotation Digital Computer is achieved by threearrangements proceeding by unrolled CORDIC and MUXes based CORDIC upto threestages, MUXes based CORDIC upto the fourth stage with and without pipelining.The proposed architecture for CORDIC adders, subtractors and shifters, all arereplaced by multiplexers upto the third stage and fourth stage. An 8 bit and16-bit Coordinate Rotation Digital Computer to achieving the sine functions andcosine functions perform all methods on Xilinx Spartan 3E (XC3S250E) and XilinxVirtex 6 FPGA(XC6VLX240). Compared with the unrolled CORDIC MUXes based CORDICachieves the high operating frequency and less area requires for hardwareimplementation.

Keywords: CORDIC algorithm, ration mode,Field-programmable gate arrays (FPGAs), multiplexer, pipelining


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Paper Submission Open For December 2020
UGC indexed  2017-2019
Last date for paper submission 30 January, 2021
Deadline Submit Paper any time
Publication of Paper Within 01-02 Days after completing all the formalities
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Publication Fees(6 Authors) Rs.1000    (Up to 06 Authors)