ISSN (Online) : 2456 - 0774

Email : ijasret@gmail.com

ISSN (Online) 2456 - 0774

DESIGN AND IMPLEMENTATION OF 64 BIT HIGH SPEED VEDICMULTIPLIER

Abstract

Abstract:-Multiplier is one of the key hardware blocks in most digital signal processing(DSP) systems. Typical DSP applications where a multiplier plays an importantrole include digital filtering, digital communications and spectral analysis.Many current DSP applications are targeted at portable, battery-operatedsystems, so that power dissipation becomes one of the primary designconstraints. Since multipliers are rather complex circuits and must typicallyoperate at a high system clock rate, reducing the delay of a multiplier is anessential part of satisfying the overall design.. This paper puts forward ahigh speed multiplier ,which is efficient in terms of speed, making use ofUrdhvaTiryagbhyam[1], a sutra from Vedic Maths for multiplication and halfadder for addition of partial products. The code is written in VHDL and resultsshows that multiplier implemented using Vedic multiplication is efficient interms of area and speed compared to its implementation using Array and Boothmultiplier architectures.

 Keywords: Halfadder, Array multiplier, Booth’s Multiplier, Vedic Multiplier, VedicMathematics.

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